This is a software development project requested by Herb Johnson. There is no manual available for this board. A RAM Disk is a nice tool to have in a CPM-80 system to take some of the load off the actual disk drives and to speed up software development. Here we start with just the finished board.
Observation of the board shows it provides a RAM disk of 256 KB (32 4164 RAM chips) and it provides a 20-bit binary counter (5 each 74LS193).
First, I had to reverse engineer the schematic from the board. Herb provided two boards, one unmodified and another with a lot of engineering changes. I photographed each board.
Here are pictures of the unmodified board:
Most of the writing on the board was done as part of the reverse engineering. Most of the work with the ohm meter is done on the back of the board. The single blue wire is a repair, not an engineering change!
Here are pictures of the modified sections of the modified board:
Here are pictures of the modified sections of the unmodified board for comparison:
Reverse engineering a two-sided printed circuit board requires gathering the pinouts of every unique IC used on the board, an ohm meter, paper, and pencil. It usually takes me a day or two to generate the schematic of a board this complicated. It takes time and a lot of patience!
I have the rough schematic on two pieces of paper. I will render it in a cleaner form on paper or enter it into one of the schematic programs available on the WEB. Using a KiCAD program is much cleaner then trying to read my hand-drawn schematics!
The complete schematic of the unmodified board is here. The complete schematic of the modified board is here.
With the schematic figured out, I wanted to try the unmodified board. I had to pull 4 banks of 4164s off another SDSystems memory board. With that done, I put the RAMDisk into my basic S-100 system. I addressed the board at port 40H. I had to move the RAMDISK base address to 0C0h to remove a conflict with the JadeDD at 43H in the test system.
From the schematic development, I found the board took 4 ports from the I/O map starting at the base address set in the switch. It allows reads from the base port (P0), and writes to the base (P0), base+1 (P1) and base+2 (P2) address. The board contains a 20-bit binary up/down counter formed from 5 each 74LS193s (U12-U22-U10-U23-U11). The top 16 bits of the counter can be loaded with bytes written to port P1 and P2. A read or write to port P0 will read or write a byte to that addressed by the binary counter and increment the binary counter. The bottom nibble is zeroed with any write to P1. The bottom 16 bits of the counter provide addressing for 64 KB of RAM in one bank. The next two bits select one of 4 banks of 4164 RAM chips. The last 2 bits select the board (A-D) at this port. You can use up to 4 boards to build one RAM disk containing up to 1 MB.
With the board inserted in the S-100 system, I am able to set an address in the binary counter, and read and write a series of bytes from/to the RAMDisk. This is real progress.
Software needed for this project include a RAM test for this RAM disk configuration and a modified BIOS to incorporate the RAM disk in my CPM-80 system. Dynamic RAM on these old boards needs to be thoroughly tested for faults. They are all over 30 years old!
CPM-80 uses a 128 byte sector size (2^^7). If we always zero the low 3 bits of port P1 and the lowest 4 bits of the counter are always set to 0, we are addressing cpm sectors with the remaining bits. Using just one board, we zero the top 2 bits of port P2. This leaves bits 7 to 17 to map "tracks" and "sectors". My initial scheme will be to use 256 "tracks" (bits 10-17) and 8 "sectors" (bits 7-9). Additionally, I would like this to map to the "M" drive under CPM-80. This will require special handling in the SELECT routine.
For the development I am using GB01 with the JadeDD disk controller and two DSDD 8 inch disk drives for the test system. I can actually develop the software on the system under test. Once I have the RAM disk operating, I can use it for more rapid software assembly. I will probably continue to edit software source code on my Windows box and move it to the test S-100 system with xmodem. The System is discussed here.
I have the SDSystems RAMDisk board in the operating S-100 CPM-80 system. I am currently modifying the BIOS program to utilize the RAM disk.
I have modified my standard JadeDD BIOS code to add in the RAMDisk using conditional assembly. With the RAM Disk code removed, the resulting system works correctly. With the RAM Disk code included , the resulting system signs on but fails to issue the CCP prompt. This, I suspect to be an error in the MINIT routine which is supposed to write 0E5H to all bytes of the RAM Disk.
I added some debugging to the code and found the error which was keeping the MINIT from completing. I also found an error in MCALC which I fixed.
The assembler source code for my modified JadeDD BIOS is here and the assembler listing is here. The complete OS file is here.
The RAM Drive is completely operational. I tested it by moving a source file to the M: drive and assembling it with MAC. The files created were correct when typed. The failure before had sectors mixed in the result files of MAC.
Last revised 26 November 2014.