Intel iSBC 80/10 Single Board Computer

I have reworked my site on the Multibus Machines to split the discussion of the work into seperate hardware and software sections. I have also split some of the hardware into subsections. I only put the latest version of the monitor or an operating system on this site. The older ones are out of date. I will make an effort to make the monitor program work for standalone SBC, SBC with 64K bytes or RAM, or to support the booting of one of the OSs. This will allow me to keep the material more up-to-date.

I purchased an Intel iSBC 80/10 computer board in May 2010. I had a collection of over 50 Multibus I computer boards. I wanted to build a machine around this processor board. This is as close to an MDS-800 as I could get. The MDS-800 was what CP/M-80 was developed on.


To get this board operating, I needed a multibus card cage. See the Card Cage discussion here.

The CPU card contains 1K bytes of RAM at 03C00-03FFFH. It has four 1K byte EPROM sockets (i2708) at 0000-00FFFH. The 2708s require +5V, -5V and +12V to operate.

I then placed the iSBC-80/10 into the card cage and connected a terminal to the board. After the normal fits with "standard" RS-232 I got the monitor prompt on the terminal!


I can't emphasize how important it is to have the Hardware Reference Manual for each board. Nothing is better than having the configuration information for jumpers and the schematic diagrams. The complete hardware reference manual for the iSBC 80/10 is here.

I had two iSBC 032/048/064 RAM boards each configured with 64K bytes of memory. I configured one board to provide the full 64K byte memory map. The complete hardware reference manual for the iSBC 064 is here.


The last board required to build a functional CP/M-80 or ISIS-II system is a disk controller. I own several Multibus I and iSBX controllers. I decided to use the iSBC 208 floppy controller board. The complete hardware reference manual for the iSBC 208 is here. I chose this board as it was a single and double density FDC only which would' handle 8", 5.25" and 3.5" disk drives. It uses an Intel 8272 FDC which I have had a lot of experience with.


This selection of three boards, if all operational, will provide a complete 2 MHz 8080A computer with 64K bytes of memory, serial terminal connection, a parallel printer port, and a DMA FDC for 8", 5-1/4" or 3-1/2" disk drives. It is my plan to set it up with a single 5-1/4" drive to start with. There will be some development work to get this all to work, especially software. But then, there is the fun of it.

First ROM adapter

The processor came with one 2708 EPROM which contained a simple monitor program. The source listing for the complete monitor was also provided in hard copy. I used this ROM for the initial tests. Since no modern programmer will handle the multivoltage 2708 anymore, I had to adapt a modern EPROM to the 2708 socket. I decided to build an adapter to fit in one ROM socket, accept and address 4K of a 27256 32K byte EPROM. I also wanted to be able to disable the onboard ROM and RAM to fully utilize the iSBC 064 RAM board. Intel did this on the later 8080/8085 CPU boards. I needed the extra ROM size to use a monitor I have used with Intel processors for 32 years.

Discussions with Herb Johnson brought up the need for the first program after the monitor was running to be an intensive RAM test. The memory in my board is 35 years old and is in unknown condition. At least the RAM chips are all in sockets!


1231 MST 02 July 2010

Here is the schematic of the EPROM adapter:


Here are a couple of pictures of the adapter.



I had an adapter to EPROMS I could burn. Now to port my 8085 monitor to the 8080 and the iSBC 80/10 board. The latest source code is here. Here is a screen capture of the new monitor:

New Monitor


1156 MST 09 July 2010

I needed to add a RAM test routine to my trusty monitor program. I tried to use the memory test routine from a Godbout RAM manual, but it did not work. I finally took the memory test routine from the HeathKit H8 and added it to the monitor. My 35 year old dynamic RAM chips were still good on both boards!

I was able to modify the iSBC 80/10 to disable the onboard EPROM and RAM by setting bits in the first 8255. This modification allows the CPU to see the entire 64 KB RAM space on the iSBC 064. It required adding a 74LS32 chip piggy back on A44. Two pins from A44 carried the RAM_RDY\ and ROM_RDY\ out to thru holes beside A43. I cut the two circuit traces and wired in the 74LS32. I used control signals from A3, a 74LS00 which buffers the output of the 8255. See the photographs below.




Here is a diagram of the modification:

RAM-ROM Disable

Here is a copy of the monitor running in RAM:

RAM-ROM Disable

I exercise the EPROM disable. First I configure port C for output. It disables the EPROM and we get the RAM pattern. The RAM monitor initialization wrote 1244H at 0039H. I write a 0 to port C and RAM stays in the memory map. I write a 0FFH to port C and the EPROM returns to the memory map.

I have now to write a simple loader to load a copy of the monitor at 0FC00H in RAM, pass control to it, and disable the onboard EPROM and RAM on the iSBC 80/10. Once that is working, I can add the floppy disk controller and begin talking to floppy disk drives.


1213 MST 17 July 2010

I have written the loader and modified the monitor to run in high memory (0xF000-0xFFFF). The latest listing for this new loader and monitor are here. It includes software for the iSBC-208 which was taken from the manual. The full code for the 8080 assembler driver is here and the PLM86 source code is here.

While I was working on this hardware, I also wrote a SIMH emulator for this machine. This emulator handles the iSBC-80/10 and the iSBC-064 correctly. The iSBC-208 FDC is still being debugged. It will boot a CPM image up to the A0>: prompt. It is not ready for primetime at this point. When I have a more stable iSBC-208 emulation, I will place the source on this site.


1419 MST 10 May 2011.

I decided to return to the actual hardware to continue the development of the floppy disk drivers. I have attached a pair of TEAC FD55BR 360KB 5-1/4 inch drives to the iSBC-208. A discussion of disk subsystems is located here. I am able to turn motors off and on, position heads, and sense the drive status sending commands directly to the iSBC-208 with in and out commands in the monitor. The floppy disk routines I took from the iSBC-208 manual (dr208.asm) are not working. I had to rework the hex load routine in the monitor to get it to load files at 9600 baud. With this capability, I am debugging the Intel code. The latest source code is located here.


1518 MST 21 September 2011.

I have built a disk exerciser program to drive the dr208 driver code. I have the motors turning on, drives stepping and homing, and the drive and interrupt sense routines working. This driver uses interrupts and that appears to be working correctly with one small code modification

The read sector routine is partially working. If it is given a bad drive, or bad track, or bad sector it will abort correctly. When it is given an CHS that is on the drive, the DMA controller takes control of the multibus and does not return it. Debugging continues.


1025 MST 27 September 2011.

Because of the DMA problem, I wanted a simple way to verify the read circuits, on the disk drives and the controller were operational. I implemented the read ID which reads the next address mark under the head and returns the drive, head, cylinder and sector from the mark. With DOS disks in both drives I get a random cylinder number between 1 and 9, as expected. The read circuitry is operational.

Now to find out why the DMA controller does not transfer any data. The initial values in the DMA channel 0 registers are correct. It may be a bad configuration of the DMA controller. No data is transfered off the disk to memory. Debugging continues.


1421 MST 9 October 2011.

Second ROM adapter

While working on getting the floppy drives to read a sector, I found I had placed the boards in the card cage in reverse order. Intel usually has the processor in the lowest slot, followed by RAM, then the disk contoller above that. Other boards can go above or below the controller. The iSBC 80/10 can coexist with only one other bus master. That other bus master is the iSBC 208 floppy disk controller. There is a serial bus priority scheme implimented on the card cage. The reason I placed the CPU card on top was the tall EPROM adapter I describe above. I have just replaced that by cutting 4 pins on A23 (18-21) and wiring them to A42 on the bottom of the board. Now I can put a 2732 EPROM in A23 and get the full 1000H bytes of ROM space. The ROM/RAM disable still work the same. The CPU card can now go into the bottom slot!


2030MST 3 November 2011.

The current changes and a couple of jumper wires on the backplane allowed the complete system to read either disk drive under control of a disk drive test program. I will place the test program and the new version of the monitor on the site soon.

I have gathered all the code and tools required to build an 8080 version of CPM80 just as I did for the iSBC 80/10 emulator. I have built a version of CPM80 and loaded into memory on the iSBC 80/10. It is NOT completely ported for the hardware, specifically, the iSBC 208 FDC. Being able to load the software on the actual hardware will allow me to make more rapid progress getting this machine to boot CPM80.


2321 MST 5 November 2011.

I have been able to boot CPM80 up on this system. I have the blocking/ deblocking working and am using 512 byte sectors on the floppies. I actually format them on a DOS machine as 320 KB floppies, then write the system and directory tracks out on the Intel system. I have debugged the iSBC 208 drivers (which are contained in my boot ROM) and the BIOS read code. I am still working on a BIOS write problem.

I have written a format routine but have not been able to put 9 sectors on a track. I can do eight. This routine uses the format call from the iSBC 208 driver. I will probably have to write a fromatter that talks directly with the 8272 FDC where I will be able to deal with all the gaps, not just gap3.

I have designed an interface from one of the 8255 interfaces on the iSBC 80/10 to an IDE drive. I will construct the "mangler" and begin to develop hard drive code for this system once I have the BIOS write problem fixed.

I will try and put the working code as I develop it on this site. My tools are already on the site.


1154 MST 16 November 2011.

PATA Adapter 1

I built the IDE adapter. This adapter just swaps wires between a 50-pin header plug and a 40-pin header plug. The way it is wired is shown below:

Parallel ATA Adapter

PATA            Signal          Intel		
34-Pin                          50-Pin

 1 ------------ Reset --------- 31
 2 ------------ Gnd ----------- All Even Number Pins
 3 ------------ Data7 --------- 35
 4 ------------ Data8 --------- 5
 5 ------------ Data6 --------- 37
 6 ------------ Data9 --------- 7
 7 ------------ Data5 --------- 39
 8 ------------ Data10 -------- 9
 9 ------------ Data4 --------- 41
10 ------------ Data11 -------- 3
11 ------------ Data3 --------- 49
12 ------------ Data12 -------- 11
13 ------------ Data2 --------- 47
14 ------------ Data13 -------- 13
15 ------------ Data1 --------- 45
16 ------------ Data14 -------- 15
17 ------------ Data0 --------- 43
18 ------------ Data15 -------- 17
19 ------------ Gnd ----------- All Even Number Pins
20 ------------ Key ----------- N/C
21 ------------ DMARQ --------- N/C
22 ------------ Gnd ----------- All Even Number Pins
23 ------------ DIOW\ --------- 31
24 ------------ Gnd ----------- All Even Number Pins
25 ------------ DIOR\ --------- 29
26 ------------ Gnd ----------- All Even Number Pins
27 ------------ IORDY --------- N/C
28 ------------ CSEL ---------- N/C
29 ------------ DMARK\ -------- N/C
30 ------------ Gnd ----------- All Even Number Pins
31 ------------ INTRQ --------- N/C
32 ------------ IOCS16\ ------- N/C
33 ------------ DA1 ----------- 21
34 ------------ PDIAG\ -------- N/C
35 ------------ DA0 ----------- 19
36 ------------ DA2 ----------- 23
37 ------------ CS1FX\ -------- 27
38 ------------ CS3FX\ -------- 25
39 ------------ DASP\ --------- N/C
40 ------------ Gnd ----------- All Even Number Pins

I used a 74LS00 in A9 and placed SBC 902 1K resistor networks in A7, A8, A10, A21 and A11. I used a short 8-inch disk cable to connect the adapter to the CPU card. I used a regular PC PATA cable to connect the drive to the adapter. Also note I had to provide 5 VDC on the adapter to add a 10K pullup resistor from /CS1 to 5 VDC. Without this resistor, operation was very erratic. There are no pullups on the PATA bus.

I have not yet modified the BIOS to use the hard disk. I have been working to get the floppy system working correctly. I need to finalize the floppy disk format for double sisded operation and build some boot disks first.

Here are some pictures of the IDE mangler.



PATA Adapter 2

I modified the PATA adapter to eliminate the requirement for power. The pin from 8255 port C0 was not used. This pin had a 1K pull up resistor on it, so I connected it in place of the 10K resistor and power connector.

Here is a close up of the CPU board modification to use a 2732 EPROM in A23.


Basically, I cut the connections for pin 19 through 22 on A23 and wired the connections to pins of A22 just as the adapter did. This modification allows the CPU to go in the bottom slot of the multibus cage and places the SBC 208 on top where it belongs. This was required to get reliable FDC operation.

The modification to enable/disable onboard ROM/RAM remains as it was.


1529 MST 24 November 2011.

I have modified the 7 slot multibus cage to use the same power connector as the 3 slot cage. I am now using it with the three board system.

I have the system now booting up CPM80. There is a bug in the ROM boot routine but bootv02 runs properly from 0x7E00 in memory. Some of the CPM80 utilities are working correctly including DDT, PIP and STAT. Currently, ASM is not assembling a file correctly. I may have a corrupted ASM file image. I will continue to test CPM80 executables and place them in a file on the Web once I get them working.

I have writtten a program to convert CPM80 .COM files to Intel .HEX file. I am using the monitor to load the com files onto the iSBC system. Then I restart CPM80 and use the SAVE command to place the file on a floppy disk. I am also trying to get Xmodem Version 5.0 to work on the system. With this, I can actually transfer any file to/from the CPM80 file system from/to the PC I use for testing and system cross-assembly.

I have been looking at the software from the iPDS system. It contains the most recent version of ISIS-II. I want to be able to boot ISIS on this system in native mode. To do this, I will have to disassemble the some of the operating system files to replace the I/O routines with ones that match my system. This will be a time consuming process.

I will also be trying to use this chassis to get one of the 8086 process boards operating. I will report results on the iSBC-86/12 or iSBC-86/30 pages.


1644 MST 14 December 2011.

I have returned to work on the 80/10 CPU. I got the dual 5.25 DSDD drives working and back in their box. I am in the process of configuring a DC-37 D-shell cable to carry data and power to the drive box. I ran into some problems with the drive cables, so I am redoing them all at this time.

I also tried a pair of SamSung SFD-321B 3.5 inch drives on this machine. I had to change the Disk Parameter Block for the increased size. I also had to modify one drive to respond as drive 0. The drives work fine and give me 700K bytes per drive. The disk controller only handles SD and DD, so no HD on this system.

Again, a discussion of the disk subsystems is found here.


1400 MST 6 January 2012.

I need to figure out the problem with the disks and CPM-80. I still cannot assemble DUMP.ASM on the system. There has to be an error saving large file on the disk. I also need to fine tune the disk skew factor. The skew of 3 works far better on the 3.5" drives than it does on the 5.25" drives. This is shown in slow loads and stores to/from the disk.


1542 MST 11 January 2012.

Here is a picture of the system on the work bench.



1308 MST 12 January 2012.

I created a test file in ASCII text to check the blocking/deblocking and sector translation. One of the files is large enough to be several blocks long and require writing and reading from multiple tracks and heads. This test performed flawlessly on the current system. The code can be found here.

I have found and corrected the errors with the format program for the 5.25" drives. This version will format a floppy disk in drive A DSDD with 9 512 byte sectors on 40 cylinders. The code can be found here.


1407 MST 24 January 2012.

I found I had a label that was multiply defined and my assembler did NOT catch it in the CCP. I corrected this and now the CCP displays messages correctly. The corrected source code can be found in the CPM-80 Operating System page.


2011 MST 31 January 2012.

I have been pondering on the motor turn on/turn off problem. I believe a simpler answer to modifying the board for an interval timer would be to leave the turn on as it is and put a timing loop in the CIN routine to count down while waiting for a character. I will try and impliment this this afternoon.


1230 MST 1 February 2012.

I have implimented the new motor on/off with the old trick of doing the countdown of a timer in the loop waiting for a character to be typed. It is working fine and is implimented in the current version of the monitor code.

With the motor problem corrected, I reevaluated the sector skew on the 5.25-inch drives. I used ASM.COM and DUMP.ASM to time the disk operations. I assembled DUMP.ASM and timed the complete operation. Before, without the corrected motor control, this operation took over a minute at any skew factor. WIth the fix, a skew of 2 took 38 seconds, a skew of 3 took 37 seconds, and a skew of 4 took 39 seconds. The skew of three is in the current CPM-80 source files, now. If I find the iSBC 86/30 CPU works better at either a skew of 2 or 4, I can change it for CPM-80 without much change in system speed.


1828 MST 1 February 2012.